Electronic components such as semiconductor chips are mounted on a wiring substrate. Such a wiring substrate is manufactured through a build-up process so that the density of wiring patterns is increased. The build-up process alternately stacks wiring layers and insulation layers. Japanese Laid-Open Patent Publication No. 2016-29697 describes a related art wiring substrate. In the wiring substrate, a high-density wiring layer, which includes an insulation layer formed from a photosensitive resin, is formed on a low-density wiring layer, which includes an insulation layer formed from a thermosetting resin.
FIG. 19 is a partially enlarged cross-sectional view of a related art wiring substrate. A wiring substrate 200 includes a low-density wiring layer 210 and a high-density wiring layer 220. The wiring layer 220 is stacked on the upper surface of an uppermost insulation layer 211 of the low-density wiring layer 210. The insulation layer 211 is formed from an insulative resin, the main component of which is a thermosetting resin. The high-density wiring layer 220 has a structure in which a wiring layer 221, an insulation layer 222, a wiring layer 223, an insulation layer 224, a wiring layer 225, an insulation layer 226, and a wiring layer 227 are sequentially stacked on the upper surface of the insulation layer 211. The wiring layer 221 and the wiring layer 223 are electrically connected by a via wiring V1 which extends through the insulation layer 222 in the thickness-wise direction. The wiring layer 223 and the wiring layer 225 are electrically connected by a via wiring V2 which extends through the insulation layer 224 in the thickness-wise direction. The wiring layer 225 and the wiring layer 227 are electrically connected by a via wiring V3 which extends through the insulation layer 226 in the thickness-wise direction. The insulation layers 222, 224, 226 are formed from an insulative resin, the main component of which is a photosensitive resin.
To limit adverse effects on the insulation property caused by electromigration, a protective film 230 is partially formed on the surface of each of the wiring layers 221, 223, 225. The protective films 230 mainly cover fine wiring portions. The surfaces of the wiring layers 221, 223, 225 exposed from the protective films 230 are formed as rough surfaces 221R, 223R, 225R, respectively. The rough surfaces 221R, 223R, 225R are located on wiring portions having large surface areas such as a plane layer or a land. The formation of the rough surfaces 221R, 223R, 225R increases the adhesiveness of the wiring layers 221, 223, 225, which include the high-density wirings, and the insulation layers 222, 224, 226.
In the wiring substrate 200, the bottoms of the via wirings V1 to V3 are respectively connected to the rough surfaces 221R, 223R, 225R. With this structure, voids tend to be formed in boundary surfaces of the rough surfaces 221R, 223R, 225R and the bottoms of the via wirings V1 to V3. For example, voids tend to be formed in boundary surfaces of metal barrier films defining the bottoms of the via wirings V1 to V3 and irregular surfaces of the rough surfaces 221R, 223R, 225R. Such voids may lower the connection reliability of the wiring layers 221, 223, 225 and the via wirings V1 to V3.